叠层芯片结构QFN封装导电胶分层失效行为分析

Analysis of delamination failure behavior of QFN packaging conductive adhesive with laminated chip structure

导电胶分层作为封装失效问题,一直受到广泛的关注。基于ANSYS平台,对导电胶剥离应力仿真,用来评估导电胶在封装和测试过程中分层风险,并进一步分析了顶部芯片、绝缘胶厚度以及导电胶厚度对导电胶分层的影响。结果表明:导电胶在可靠性测试阶段125℃冷却到室温阶段最容易发生导电胶分层失效。该款封装中导电胶分层的原因是顶部叠层芯片结构引起的。通过对顶部芯片、绝缘胶的厚度进行设计,发现其厚度越薄导电胶的剥离应力越小,分层风险越小。导电胶的厚度在10μm时,胶体的粘附力最大,剥离应力最小,导电胶分层风险最小。

Conductive adhesive delamination,as a package failure problem,have been receiving wide attention.Using ANSYS platform,the peeling stress was simulated to evaluate the delamination risk of the conductive adhesive during packaging and test.The delamination of conductive adhesive was further analyzed by considering the thickness effect of top chip,insulating adhesive and conductive adhesive.The results show that the delamination failure most likely happens during cooling from 125℃to room temperature.The delamination of the conductive adhesive is mainly caused by the top laminated chip structure.Thinner top chip and insulating adhesive can reduce the delamination risk of the conductive adhesive.When conductive adhesive is 10μm,the delamination failure is obviously improved by adhesion force and peeling stress.