单界面陷阱对7nm P型GAAFET性能影响研究

Study on the Effect of Single Interface Trap on Performance of 7nm P-Type GAAFET

采用3D TCAD软件仿真分析了单界面陷阱对7 nm P型全环栅场效应晶体管DC和AC性能的影响。研究结果表明:单个陷阱能使转移特性曲线发生严重偏移;当单界面陷阱位于沟道中心附近且陷阱能级靠近导带时,对关态电流和阈值电压的影响最大;陷阱使栅电容的相对变化量小于1%;环栅晶体管沟道长度和纳米线直径的缩小会加重陷阱对器件性能的影响,高介电常数材料的Spacer可减小陷阱引起的沟道能带弯曲程度,从而缓解陷阱对器件性能的影响。在调节器件结构参数使器件性能最大化的同时,应使陷阱对器件性能的影响最小化。

The DC and AC performance of P-type gate-all-around field effect transistor(GAAFET) at 7-nm node affected by single interface trap were investigated by 3 D TCAD simulation. It was found that the transfer characteristic curve suffered significant shift due to single trap. When single interface trap located at the middle of channel and trap energy level was closed to conduction band, the largest variation of off-state current and threshold voltage was observed. The gate capacitance variation induced by trap was less than one percent. The impact of trap on device performance was aggravated by the reduction of channel length or nanowire diameter of GAAFET. The channel energy band bending caused by trap was decreased by spacer with high dielectric constant, so the effect of trap on device performance was reduced. Both maximizing device performance and minimizing the variations caused by interface trap should be considered when modulating device structure parameter.