一种基于可编程流水线型时间-数字转换器的全数字锁相环

An All-digital Phase-locked Loop with a Programmable Pipeline Time-to-digital Converter

提出了一种基于可编程流水线型时间-数字转换器的全数字锁相环。时间-数字转换器使用可编程增益时间放大器实现两级时间量化。补偿器用于校正可编程增益时间放大器的增益误差。低压数控振荡器使用电流复用结构来降低功耗,并使用桥接电容技术来提高频率分辨率。该全数字锁相环采用65 nm CMOS技术进行制造,测量结果表明,带内和带外相位噪声分别为-90 dBc/Hz@10 kHz偏移和-130 dBc/Hz@1 MHz偏移。RMS和峰峰值抖动分别为1.24 ps和8.65 ps。

An all-digitally phase-locked loop(ADPLL)with a programmable pipeline time-todigital converter(TDC)was proposed. Two-step time quantization of TDC was realized by employing a programmable-gain time amplifi er(PGTA). In consideration of the gain error of PGTA,the compensator is designed to correct it. The low-voltage digital-controlled oscillator uses current-reused structure to reduce power consumption,and uses bridging-capacitance technology to improve frequency resolution. The proposed ADPLL was fabricated by a 65 nm CMOS technology. The measurement results show that the in-band and out-band phase noise are -90 dBc/Hz @ 10 kHz offset and-130 dBc/Hz@1 MHz offset,respectively. The RMS jitter and peak-to-peak jitter are 1.24 ps and 8.65 ps,respectively.