基于FPGA的汽车雷达信号处理算法的高级综合与评估

High Level Synthesis and Evaluation of an Automotive RADAR Signal Processing Algorithm for FPGAs

高层次综合(High Level Synthesis,HLS)是一种使用诸如C/C++等高级语言来设计和开发硬件(Hardware,HW)的技术。一种汽车雷达信号处理算法的HLS模型已经被开发出来且作为HLS模型和现有的硬件描述语言(Hardware Description Language,HDL)模型之间的对比。尽管HLS目前相当地受欢迎,但是用来评估HLS的应用程序往往很小。使用基于HLS的设计方法学综合设计出了一个汽车雷达信号处理系统,该系统具有中到高的复杂度,把综合结果与基于RTL的设计进行比较。使用了许多技术使高级程序模型准备好进行综合,同时优化速度和Xilinx Vivado HLS计算机辅助设计(Computer-Aided Design,CAD)工具的资源使用情况。与基于RTL的设计相比,该课题实现了2倍的加速,同时使得设计时间从大约16周减少到6周。FPGA的资源利用率虽然增加但仍低于FPGA可用总资源的5%。

High Level Synthesis(HLS)is a technology that USES advanced languages such as C/C++to design and develop Hardware(HW).An HLS model of an automotive radar signal processing algorithm has been developed as a comparison between the HLS model and existing Hardware Description Language(HDL)models.Although HLS are currently fairly popular,the applica⁃tions are used to evaluate HLS tend to be small.At present,an automotive radar signal processing system based on HLS design meth⁃odology is designed comprehensively.The system has medium to high complexity.The results of our synthesis are compared with the design based on RTL.So many technologies are used to make the advanced programming model ready for integration,while optimiz⁃ing the speed and resource usage of Xilinx Vivado HLS computer-aided Design(CAD)tools.Compared to the RTL based design,this project achieves twice the acceleration and reduces the design time from approximately 16 weeks to 6 weeks.Although the re⁃source utilization of FPGA is increased,it is still less than 5%of the total resources available to FPGA.