基于向量排序法的数字集成电路功耗测试仿真

Digital Integrated Circuit Power Test Simulation Based on Vector Sequencing

传统数字电路功耗测试方法存在结果误差大、耗时长的问题,提出基于向量排序法的数字集成电路功耗测试方法。方法深入研究了数字集成电路布尔值及逆变器的动、静态功耗,获取每个逻辑门由于状态变化而产生充放电所消耗功率的功耗模型,通过内部与各输入口的相互影响确定其参数。根据相应的汉密尔顿图优化向量排序法,最后实现对该电路的功耗测试。设计基于ISCA系列电路的仿真,实验验证了所提方法的功耗测试具有有效性,且测试结果精准度较高,耗时更短。

Traditionally,the method has the problem of large error and high time consumption.Therefore,a meth⁃od for testing the power consumption of digital integrated circuit based on vector ordering method was proposed.This method studied the Boolean value of digital integrated circuit and the dynamic and static power consumption of invert⁃er,and built the power consumption model of the power consumed by charging and discharging of logic gate due to the state change.Moreover,the parameters were determined by the interaction between its interior and input port.In addi⁃tion,the vector ordering method was optimized by Hamilton diagram.Finally,the test for power consumption of cir⁃cuit was achieved.The simulation experiment based on ISCA circuits was designed.The experiments verify the effec⁃tiveness of the proposed method in testing power consumption,and the test result has higher accuracy and shorter time.