具有SLA结构的12位并行计数器架构的设计

Design of 12-bit Parallel Counter Architecture with SLA Structure

针对高速电路中的高工作频率,低功耗且避免产生毛刺的需求,设计了的具有SLA结构的12位高速并行计数器。SLA结构使得工作频率相比于传统计数器更高,且避免产生毛刺。触发器是使用13个晶体管来实现的TSPC型D触发器,它所含晶体管数目少且速度快。该设计使用80 nm CMOS工艺,Cadence Virtuoso和HSPICE实现。结果表明:设计的计数器最差情况下工作频率为1.03 GHz,平均功耗为169.13μW。

Aiming at the requirements of high working frequency,low power consumption and avoiding burrs from competition and risk in high-speed circuits,a 12-bit high-speed parallel counter with SLA structure was designed.The SLA structure makes higher working frequencies than traditional counters and avoids burrs.The flip-flop uses 13 transistors to realize the true single-phase clock(TSPC)D flip-flop and it has a small number of transistors and a fast speed.The design is implemented using 80 nm CMOS technology,Cadence Virtuoso and HSPICE.The results show that the worst case working frequency of the designed counter is 1.03GHz and the total average consumption is 169.13μW.