基于AlON的4H-SiC MOS高k栅介质电性能

Electric Characteristics of 4H-SiC MOS High-k Gate Dielectrics Based on AlON

提高栅介质的界面质量和可靠性一直是功率碳化硅金属氧化物半导体(MOS)器件研发的核心任务之一。基于原子层沉积(ALD)技术,在n型4H-SiC上沉积了Al基高介电常数(k)栅介质材料AlON。在不同沉积后退火(PDA)温度下制备了AlON/4H-SiC MOS电容,对制备的AlON/4H-SiC MOS电容进行了高-低频电容-电压特性测试,并开展了介质零时击穿(TZDB)实验。发现当PDA温度为800℃时,得到的AlON/4H-SiC MOS电容有着较低的界面态密度、栅极电流密度和较高的介电击穿电场强度,表明经过合适的PDA工艺后,基于AlON高k栅介质材料的4H-SiC MOS器件栅介质的界面态密度得到显著降低,栅介质的介电性能和可靠性得到提高。

One of the key missions for researching and developing SiC power metal oxide semiconductor(MOS)devices is to improve the interface quality and reliability of gate dielectrics.Based on atom layer deposition(ALD)technique,Al-based high-dielectric constant(k)AlON gate dielectric materials were deposited on n-type 4H-SiC.Under different post-deposition annealing(PDA)temperatures,AlON/4H-SiC MOS capacitors were prepared.The high-low frequency capacitance-voltage characteristic test and time-zero-dielectric breakdown(TZDB)test of the prepared AlON/4H-SiC MOS capacitors were carried out.It is found that when the PDA temperature is 800 ℃,the obtained AlON/4H-SiC MOS capacitors have lower interface state density,lower gate current density and higher dielectric breakdown electric field intensity.The result shows that through proper PDA process,the gate dielectric interface state density of the 4H-SiC MOS devices based on AlON high-k gate dielectric materials is significantly reduced,and the dielectric property and reliability of the gate dielectrics are improved.