期刊文献+

基于FPGA的查表式运算器的设计

下载PDF
导出
摘要 本文所研究的查表式运算器主要由四个结构构成,包括计算、存储、输入、显示等,计算功能包括加、减、乘、除等,其中用3个存储器来实现存储功能。
作者 金天星 闵啸
出处 《电子技术与软件工程》 2020年第16期104-105,共2页 ELECTRONIC TECHNOLOGY & SOFTWARE ENGINEERING
  • 相关文献

参考文献5

二级参考文献23

  • 1[1]R Pillai,D Al-Khalili,A Al-Khalili.A Low Power Approach to Flo ating Point Adder Design[C].In:Proceedings of the IEEE International Conference on Computer Design :VLSI in Computers and Processors,ICCD'97,1997-10
  • 2[2]J Bruguera,T Lang. Leading-One Prediction Scheme for Latency Im-provement in Single Datapath Floating-Point Adders[C].In:Proc 1998 IEEE Conference on Computer Design (ICCD98), 1998-10: 298~305
  • 3[3]A Beaumont-Smith,N Burgess,S Lefrere et al.Reduced Latency IEEE Floating-Point Standard Adder Architectures[C].In: 14th IEEE Sympo sium on Computer Arithmetic,Adelaide,Australia,1999:35~42
  • 4[4]G Even,W J Paul.On the Design of IEEE Compliant Floating Point Units[J].IEEE Trans on Computers,2000;49(5):398~413
  • 5[5]J D Bruguera,T Lang. Using the Reverse-Carry Approach for DoubleDatapath Floating-Point Addition[C].In:Proceedings of 15th Sympo- sium on Computer Arithmetic(ARITH15).Vail,Colorado(USA),2001-06
  • 6[6]A Jaenicke,W Luk.Parameterised Floating-Point Arithmetic on FPGAs [C].In:IEEE International Conference on Acoustics,Speech,and Signal Processing, USA, 2001; 2: 897~900
  • 7[7]S F Oberman,M J Flynn. A Variable Latency Pipelined FloatingPoint Adder[C].In: Proceedings of Euro-Par'96, Lyon, France,Springer LNCS, 1996-08; 1124: 183~ 192
  • 8[8]S F Oberman. Design Issues in High Performance Floating Point Ari thmetic Units[D].Ph D thesis. Stanford University,1996
  • 9夏宇闻.Verilog数据系统设计教程[M].北京:北京航空航天大学出版社,2008.
  • 10Xilinx,Inc..Virtex-6 FPGA Family[EB/OL].(2010-01-12).http://www.xilinx.com/products/virtex6/.

共引文献10

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部