一种4 Gsample/s12bADC接口电路中的发送器设计

Design of Transmitter in a 4 Gsample/s 12 b ADC Interface Circuit

针对一种4 Gsample/s12b模数转换器(Analog-to-Digital Converter,ADC)中的接口电路发送器的设计难度大的问题,基于吉比特收发器(Gigabit Transceiver,GTX),遵循JESD204B子类1标准,设计并验证了一种四字节并行发送器。采用四字节并行方案实现8B/10B编码器和加扰器,将系统时钟由1 GHz降至250 MHz,降低了设计难度;通过添加均衡指示位,提高了电路最大工作频率。基于赛灵思ZC706开发板,完成了该发送器与接收端IP的联合验证。实验结果表明,接收数据与发射数据一致且通道间数据无偏移,该发送器满足4 Gsample/s 12 b ADC接口电路的传输带宽需求。相同处理效果下,相比单字节、双字节设计方案资源占比更少。

In order to solve the difficulty of designing the interface circuit transmitter in a 4 Gsample/s 12 b analog-to-digital converter(ADC),a four-byte parallel transmitter is designed and verified based on the Gigabit transceiver(GTX)and the JESD204B subclass 1 standard.The 8B/10B encoder and scrambler are realized by using four-byte parallel scheme,which reduces the system clock from 1 GHz to 250 MHz and reduces the design difficulty.The maximum working frequency of the circuit is increased by adding balanced indicator bit.Based on the development board of Xilinx ZC706,the transmitter and the receiver IP are both verified.The experimental results show that the received data is consistent with the transmitted data and there is no offset between channels.The transmitter meets the transmission bandwidth requirements of 4 Gsample/s 12 b ADC interface circuit.Compared with that of single-byte and double-byte design schemes,the resource share is less under the same processing effect.