基于FPGA的LDPC编译码的高速并行化设计与实现

Design and Implementation of High-Speed Parallelization of LDPC Codec based on FPGA

LDPC码是一种特殊的线性分组码,其性能可接近于香农限。由于LDPC码具有良好的性能且译码复杂度低、结构灵活,已广泛应用于信道编码领域,包括深空通信、光纤通信、卫星数字视频和音频广播等领域。采用可配置的全并行结构,在FPGA实现LDPC编译码时提高了数据处理能力,并根据芯片的资源大小进行不同方式的并行化译码结构处理。经过ModelSim仿真验证和在Artix-7平台上试验,验证了LDPC译码可配置并行化实现的可行性和有效性,同时对比验证了它在硬件资源上的消耗和多场景多种速率情况下的数据传输性能。

LDPC code is a special linear block code whose performance can be close to the Shannon limit.Because of its good performance,low decoding complexity and flexible structure,LDPC code has been widely used in the field of channel coding,including deep space communications,optical fiber communications,satellite digital video and audio broadcasting.The use of a configurable full parallel structure improves the data processing capability when implementing LDPC encoding and decoding on FPGA,and performs parallel decoding structure processing in different ways according to the size of the chip’s resources.ModelSim simulation and experiments on the Artix-7 platform indicate the feasibility and effectiveness of LDPC decoding configurable parallel implementation.In addition,its consumption of hardware resources and its data transmission in multiple scenarios and multiple rates are compared and verified.