一个转换时间280 ns的10 bit两级流水线式循环ADC设计

Design of a 10 bit 280 ns Conversion Time Two-stage Pipelined Cyclic ADC

设计了一款用于大分辨率高帧率图像传感器的10 bit列并行ADC。该ADC为两级循环式流水线结构,其中第一级ADC集成了相关双采样放大器功能,用于实现对像素输出电压的去噪和放大。两级ADC还采用了新型的前馈补偿式两级运放来改善动态建立特性并降低功耗。采用90 nm CMOS工艺进行流片制作,单个ADC面积为5μm×1 150μm。测试数据表明,ADC的微分非线性(DNL)为+0.78/-0.65 LSB,积分非线性(INL)为+1.63/-4.12 LSB,功耗为105μW。

A 10-bit column-parallel ADC for high resolution and framerate image sensor was designed.The ADC adopted two-stage pipelined cyclic ADC.The first stage integrated the function of correlated double sample to remove noise and implement amplification to the pixel output voltage.In addition,two-stage ADC adopted a new feedforward compensation two-stage operational amplifier for better settling behavior and lower power consumption.The ADC is designed and fabricated in 90 nm CMOS process,and the area of single ADC is 5μm×1150μm.The measurement shows that the DNL is+0.78/-0.65 LSB,the INL is+0.1.63/-4.12 LSB,and the power consumption is 105μW.