面向嵌入式的可重构FFT的硬件实现

Hardware implementation of reconfigurable FFT for embedded system

针对实时嵌入式应用,提出了一种采用Radix-2算法的可重构FFT硬件加速器结构。该结构一次可并行处理16点FFT,且可在不改变电路结构的情况下,通过修改相应的配置信息来实现16-1024点FFT。该结构的硬件利用率为100%,整个设计采用Synopsys VCS仿真,在100 MHz工作频率下,对于1024点16位复数定点FFT仅需要38.6μs,与Cortex M4的DSP相比速度提升了94%以上。经DC综合结果表明在SMIC 0.11μm工艺中,该结构的核心面积为0.98 mm2,可用于嵌入式设备中。

For real⁃time embedded applications,a reconfigurable FFT hardware accelerator structure using Radix⁃2 algorithm is proposed.The structure can process 16 point FFT in parallel at one time,and can realize 16-1024 point FFT by modifying the corresponding configuration information without changing the circuit structure.The hardware utilization rate of the structure is 100%.The whole design adopts Synopsys VCS simulation.At 100 MHz working frequency,it only needs 38.6μs for 1024 point 16 bit complex fixed⁃point FFT,and the speed is increased by 94%compared with the DSP of Cortex M4.The DC synthesis results show that in SMIC 0.11μm process,the core area of the structure is 0.98 mm2,which can be used in embedded equipment.