摘要
分析了常见高速串行总线测试方案的优缺点,针对VPX高速背板结构和信号定义特征,提出了一种低成本的VPX背板高速串行总线的测试方法。该方法以FPGA为运算核心,通过巧妙的结构设计和高速串行电路设计,实现了单次同时测试最多16对高速收发通道,且可进行高速串行总线从物理层、链路层到协议层的信号误码率测试和眼图测试,每通道测试速率可大于10 Gb/s。
The advantages and disadvantages of common high-speed serial bus test schemes are analyzed. Aiming at the characteristics of VPX high-speed backplane structure and signal definition, a low-cost VPX backplane high-speed serial bus test method is proposed. It takes FPGA as the operation core, with ingenious structure design and high-speed serial circuit design, it can test up to 16 pairs of high-speed transceiver channels each time, and can test the signal error rate and eye chart of high-speed serial bus from physical layer, link layer to protocol layer, and the test rate of each channel can be greater than 10 Gb/s.
作者
马力科
Ma Like(China Electronics Technology Group Corporation No.10 Research Institute,Chengdu 610036,China)
出处
《电子技术应用》
2020年第10期69-72,78,共5页
Application of Electronic Technique
