基于FPGA的DDR3高速图像缓存策略

DDR3 high-speed image cache strategy based on FPGA

为满足图像处理领域多帧累计成像对高帧频、高分辨率数据的实时的采集与缓存的要求,外接大容量DDR3,并充分利用其带宽是亟待解决的问题。结合Xilinx提供的MIG_v4.0IP核,引入读写FIFO和读写逻辑控制模块,提出了一种基于DDR3的读写访问策略,可以提高DDR3带宽的利用率。测试结果表明,在DDR3 PHY接口工作频率400M的情况下,带宽利用率可达到90%以上。不失一般性,本文提出的访问策略对普通的高帧率、高分辨率图像的高速缓存同样能够提供有益参考。

In order to meet the requirements of multi-frame cumulative imaging in the field of image processing for real-time collection and buffering of high frame rate and high resolution data, it is an urgent problem to connect an external large-capacity DDR3 and make full use of its bandwidth. Combined with the MIG_v4.0 IP core provided by Xilinx, the read-write FIFO and read-write logic control module are introduced, and a read-write access strategy based on DDR3 is proposed, which can improve the utilization rate of DDR3 bandwidth. The test results show that, under the DDR3 PHY interface operating frequency of 400 M,the bandwidth utilization rate can reach more than 90%. Without loss of generality, the access strategy proposed in this paper can also provide a useful reference for the caching of common high frame rate and high resolution images.