基于最小和算法的QC-LDPC译码器的FPGA实现

Implementation of QC-LDPC decoder based on Layered min-sum algorithm

为了提高准循环低密度奇偶校验(QC-LDPC)译码器的吞吐率、迭代译码收敛速度和资源利用率,本文针对QCLDPC码校验矩阵的结构特性设计一种层间流水线结构译码器。该译码器对译码策略和校验节点更新结构进行优化,克服了传统分层译码并行所带来的数据冲突问题;各分层之间的迭代译码非串行进行,校验节点和变量节点可并行计算,有效地提高译码器的资源利用率;校验节点更新的结构在不增加运算复杂度的情况下消耗时间更短,分层最小和算法加快了迭代译码的收敛速度,压缩了单次迭代所需时间。本文以WIMAX标准(2304,1152)QC-LDPC码为例,以现场可编程门阵列(FPGA)作为实现平台,仿真并实现了基于最小和算法的QC-LDPC译码器。结果表明,当译码器工作频率为200 MHz、迭代次数为10次时,吞吐量可达到1 Gbit/s。

In order to improve the throughput,iterative decoding convergence speed and resource utilization of quasicyslic low-density parity-check codes(QC-LDPC)decoder,this paper designs an inter-layered-pipeline decoder based on the structure of QC-LDPC code check matrix.The decoder optimizes the decoding strategy and check node update structure,which overcomes the data conflict caused by parallelism of traditional layered decoding.The iterative decoding between the layers is not serial,and check nodes and variable nodes can be calculated in parallel,which effectively improves the resource utilization of the decoder.The new structure of check nodes consumes less time without increasing the operation complexity,and the layered min-sum decoding algorithm speeds up the convergence rate and reduces the time required for a single iteration.In this paper,taking(2304,1152)QC-LDPC code based on WIMAX standard as an example and field programmable gate array(FPGA)as the implementation platform,the QCLDPC decoder based on the min-sum algorithm is simulated and implemented.The result shows that the throughput can reach 1 Gbit/s when the frequency of decoder is 200 MHz and the number of iterations is 10.