用于高计数率中子检测的模拟前端的设计

Design of analog front end for high count rate neutron detection

针对具有1 nF传感电容和5μA平均幅度的随机电流脉冲的核探测器,设计了一种基于跨阻放大器(TIA)的模拟前端.核心放大器采用单端折叠共源共栅结构提高带宽和速度,采用增益增强(gain-boosted)技术以满足高增益的要求.模拟前端基于SMIC 40 nm CMOS工艺设计实现,仿真结果表明,核心放大器在电源电压1.1 V下,增益带宽积为2.2 GHz,增益为72.3 dB,模拟前端在闭环增益为500Ω和1 nF传感电容时,可以实现22 MHz的闭环带宽,模拟前端的总功耗为3.2 mW.

For a nuclear detector with a 1 nF sensing capacitor and a random current pulse with an average amplitude of 5μA,this article designs an analog front end based on a transimpedance amplifier(TIA).The core amplifier uses a single-ended folded cascode structure to increase its bandwidth and speed,and uses gain-boosted technology to achieve its high gain requirements.The analog front-end is designed and implemented based on the SMIC 40 nm CMOS process.The simulation results show that the core amplifier has a gain-bandwidth product of 2.2 GHz and a gain of 72.3 dB at a power supply voltage of 1.1 V.When the analog front-end has a closed-loop gain of 500Ωand a 1 nF sensing capacitor,it has a closed-loop bandwidth of 22 MHz,the total power consumption of the analog front-end is 3.2 mW.