一种逐次逼近寄存器型模数转换器

A Successive Approximation Register Analog-to-Digital Converter

设计了一种逐次逼近寄存器型模数转换器(SAR ADC)。提出了一种新型全动态钟控比较器结构,消除了比较器的亚稳态误差,解决了ADC输出不稳定的问题,实现了失调和噪声之间良好的折中,提升了ADC的动态性能;设计了一种全新的自举开关,在确保采样保持电路性能的同时提高了其可靠性;提出了一种新颖的正反馈结构的动态逻辑单元,并应用在逐次逼近逻辑电路中,在降低功耗的同时消除了误码问题;改进了共模电平产生电路结构,提高了共模电平的产生速度和稳定性。电路采用0.18μm DB S-BCD工艺设计实现,芯片面积约为360μm×560μm,10 bit分辨率模式下的功耗和信噪失真比(SNRD)分别为21.1μW和58.64 dB。

A successive approximation register analog-to-digital converter(SAR ADC)was designed.A new clock-controlled full dynamic comparator structure was presented,the meta-stability error of the comparator was eliminated,and the unstable problem of ADC output was solved,therefore a compromise between offset and noise was realized,and the dynamic performance of the ADC was improved.A new bootstrap switch was designed to ensure the performance and to improve the reliability of the sample-and-hold circuit.A novel dynamic logic cell with a positive feedback structure was presented and used in the successive approximation logic circuit,and bit errors were eliminated while the power consumption was reduced.The common-mode level generation circuit structure was improved for improving the generating speed and the stability of the common-mode level.The circuit chip with an area of about 360μm×560μm was designed and fabricated in 0.18μm DB S-BCD process.The power consumption and signal to noise distortion ratio(SNRD)in 10 bit mode is 21.1μW and 58.64 dB,respectively.