DDR3堆叠键合组件的信号完整性分析与优化

Signal Integrity Analysis and Optimization of DDR3 Stacked Bonding Module

对一种DDR3芯片堆叠键合的内存组件的封装和基板设计进行信号完整性分析和优化。采用在等效电路模型上进行参数扫描的方法,对基板DDR3传输线的分段阻抗和延时进行参数优化。结果表明,优化阻抗和延时的设计可使信号眼高增加,从而改善信号质量,其原因与容性负载补偿有关。从信号波形眼图和时序分析结果可知,该设计符合JEDEC标准。

Signal integrity analysis and optimization were performed on the packaging and substrate design of a DDR3 die-stacking bonding memory module.The sectional line impedance and delay parameters are scanned on the equivalent circuit model for DDR3 transmission line.The results show that the optimized impedance and delay settings increase the signal eye height and therefore improve the signal quality,which is attributed to the capacitive load compensation.According to the signal eye diagram and the timing analysis results,the design conforms to JEDEC standard.