32 nm CMOS工艺单粒子三点翻转自恢复锁存器设计

Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology

纳米尺度CMOS工艺的电荷共享效应日益显著,粒子入射导致电路内部多个节点同时翻转的概率急剧升高.为了提高时序单元的可靠性,提出了一种三点翻转(triple node upsets,TNUs)自恢复的加固锁存器结构,利用双输入反相器的阻塞能力,将24个双输入反相器级联成6级,经反馈将发生翻转的节点恢复正确;内部采用不对称的连线方式,有效地消除了共模故障,优化了双输入反相器内部NMOS/PMOS的驱动能力,消除了节点逻辑值翻转造成的亚稳态.采用Hspice进行实验表明,相比已有容忍TNUs的4种加固锁存器,仅有所提结构和TNURL可以从TNUs中自行恢复,其他3种加固锁存器均无法从TNUs中自行恢复,而且会在输出端产生高阻态;和TNURL结构相比,所提结构的功耗减小了35.3%,延迟减小了48.3%,功耗延迟积(power delay product,PDP)减少了67.6%.

The charge sharing effect of nanoscale CMOS technology is becoming more and more significant, and the probability of multiple nodes upset simultaneously caused by particle incidence increases sharply. In order to improve the reliability of sequential units, a triple node upsets(TNUs) self-recovery hardened latch structure is proposed. By using the blocking ability of dual input inverters, and placing 24 dual input inverters into six stages, the upset nodes are recovered correctly by feedback;In addition, the internal asymmetric connection mode is used to eliminate the common mode fault;and the driving ability of NMOS/PMOS in the dual input inverter is optimized, which can eliminate the metastable state caused by the inversion of the node logic value. Experiments with Hspice show that, compared with the existing four types of hardened latches that tolerate TNUs, only the proposed structure and TNURL can self-recover from TNUs. The other three hardened latches cannot recover from TNUs by itself, and will produce a high impedance state at the output;Compared with the TNURL structure, the power consumption of the proposed structure is reduced by 35.3%, the delay is reduced by 48.3%, and the power delay product is reduced by 67.6%.