基于0.18 μm CMOS工艺的高精度低功耗比较器电路设计

Design of high precision low power comparator circuit based on 0.18μm CMOS process

比较器作为模数转换电路关键模块之一,其速度、精度、功耗等性能决定了ADC电路的整体性能。应用于不同类型的ADC结构的比较器电路,对其性能参数有着不同的要求。文章提出了一种基于预放大再生锁存理论,应用于SAR ADC(逐次逼近型模数转换)结构的比较器,该比较器达到了高精度,低功耗等高性能要求,在1.8V电源供电下,时钟频率为2 MHz时,该比较器的分辨率达到1 mV,平均功耗为0.3 mW。

As one of the key modules of analog-to-digital conversion circuit,the speed,precision and power consumption of comparator determine the overall performance of ADC circuit.Comparator circuits with different types of ADC structures have different requirements for their performance parameters.A kind of comparator based on preamplifier regenerative latch theory is proposed in this paper,which is applied to SAR ADC(successive approximation A-D conversion)structure.The comparator has achieved high precision,low power consumption and other high performance requirements.When the clock frequency is 2 MHz,the resolution of the comparator is 1 mV,and the average power consumption is 0.3 mW.under the power supply of 1.8 power supply.