一种低开销高性能的RISC-V处理器设计

Design of Low-cost High-performance RISC V Processor

随着无线连接、大数据、人工智能技术的快速发展,嵌入式领域的设备开始具备更多的感知能力和更灵活的网络连接功能。从应用的发展趋势来看,这些设备不仅需要超低功耗,而且需要具备更强大的数据采集和处理能力。基于性能和功耗的折中要求,本文提出了一种低开销、高性能、顺序取指、乱序执行的RISC-V处理器架构。首先详细介绍了各级流水线之间的结构和内在逻辑关系,最后对处理器的性能做了跑分测试。

With the rapid development of wireless connections,bit-data and artificial intelligence,devices in embedded field are beginning to have more perceptive capabilities,and more flexible network connection.Viewed from the developing trends of embedded application,the embedded devices require not only low power consumption,but also the strong ability of data collection and handling.As to meet the compromising requirement between power and performance,an out-of-order RISC V processor with low-cost and high-performance is designed.At first microstructure and logical relationship of each pipeline are introduced.And the performance of the processor is tested and analyzed at last.