ETC中FM0编码的一种实现方式——基于FPGA的FM0编码仿真技术研究

An Implementation of FM0 in ETC

中国ETC系统采用专用短程通信技术协议来完成整个通信过程,该协议规定了基带编码采用FM0编码,讨论使用了INTEL公司的CYCLONE系列FPGA通过VERILOG语言在QuartusⅡ软件上实现FM0编码,并使用Modelsim软件进行仿真,验证了编码实现方法的正确性和有效性。

In China’s Electronic Toll Collection(ETC) system, the Dedicated Short Range Communication(DSRC) protocol, which specifies that the baseband coding adopts FM0, is used to complete the whole communication process. This paper discussed that using CYCLONE series FPGA from Intel Corporation to implement FM0 coding on Quartus Ⅱ software through VERILOG language, and Modelsim software was used to simulate, which verified the correctness and effectiveness of the coding implementation method.