高性能CMOS鉴频鉴相器和电荷泵的设计

Design of high⁃performance CMOS phase frequency detector and charge pump

在最近几代通信系统设计中,锁相环已经成为实现频率合成器的标准方法。采用TSMC 0.18μm CMOS工艺,设计了一款应用在芯片级铷原子钟3.4 GHz激励源中的鉴频鉴相器和电荷泵电路。鉴频鉴相器由两个边沿触发、带复位的D触发器和一个与门组成。为了消除死区,在复位支路又加入了延时单位。电荷泵采用电流镜结构设计,有效地抑制了电流失配,进一步降低了输出信号的噪声。测试结果表明,在电源电压为1.8 V,电荷泵电流为50μA时,充放电电流最大失配仅为2.2μA,输出相位噪声为-145 dBc/Hz@1 MHz。

In the design of several generations of communication systems,phase⁃locked loops have become the standard method to realize frequency synthesizers.Based on TSMC 0.18μm CMOS process,a phase frequency detector and charge pump circuit which is applied to atomic clock’s 3.4 GHz excitation source is designed.The phase frequency detector consists of two edge⁃triggered,resettable D flipflops and an AND gate.In order to eliminate the dead zone,several inverters are added to the reset branch.The charge pump adopts the current mirror,which effectively inhibits the loss of electricity and further reduces the noise of the output signal.The result shows that when the power supply is 1.8 V and the charge pump current is 50μA,the maximum difference between both charge and discharge currents is only 2.2μA and the output phase noise is-145 dBc/Hz@1 MHz.