200 MHz甚高频低相位噪声时钟信号发生电路的设计与实现

Design and Implementation of 200 MHz VHF Low Phase Noise Clock Generator

高频、低相噪的时钟信号在电子系统中处于“心脏”的地位,而现代电子技术的发展对时钟信号的工作频率和相位噪声提出了更高的要求。对比研究了两种低噪声倍频方法(直接倍频以及混频方式)的噪声特性,建立了相位噪声模型,提出了相位噪声的抑制方法,并分别设计电路进行对比验证。实验结果表明,两种电路的相位噪声指标均接近理论值,其中通过降低混频参考与本振的相关性,混频方式可改善输出的相位噪声,与理论分析一致。

Clock plays an essential role in electrical system in which higher frequency source with better phase noise performance is in increasing demand.Performance on phase noise of frequency multiplier based on delay line mixer was researched by comparison with the direct doubling.The phase noise models are established and analyzed,showing that the multiplier based on delay line mixer can obtain lower phase noise clock by minimizing the correlation between the RF input and the LO of the mixer.Test circuits are designed and implemented,and the result shows compliance with the analysis.