一种用于千兆以太网的时钟数据恢复电路设计与实现

Design and Implementation of Clock Data Recovery Circuit for Gigabit Ethernet

采用标准0.13μm CMOS工艺,设计了一种基于相位插值器的1/4速率时钟数据恢复电路,并将其应用于千兆以太网的SerDes收发器。该电路主要由高速采样电路、相位检测电路、相位选择控制电路、相位插值控制电路、相位选择器以及相位插值器等组成。相较于传统的基于锁相环结构的时钟数据恢复电路,该电路降低了数据峰峰值抖动和电路设计的复杂度。仿真结果表明,时钟数据恢复电路锁定后,恢复的时钟和数据的峰峰值抖动分别为38 ps和87 ps,满足了IEEE 802.3z协议要求。

Using standard 0.13μm CMOS technology,a 1/4 rate clock data recovery circuit based on phase interpolator is designed for SerDes transceiver of Gigabit Ethernet.The circuit is mainly composed of a high-speed sampling circuit,a phase detection circuit,a phase selection control circuit,a phase interpolation control circuit,a phase selector,and a phase interpolator.Compared with the traditional clock data recovery circuit based on the phase-locked loop structure,the data peak-to-peak jitter and circuit design complexity are reduced.The simulation results show that the clock and data recovered after the clock data recovery circuit is locked are the peak-to-peak jitter of the clock and data They are 38 ps and 87 ps respectively,which meets the requirements of IEEE 802.3z protocol.