基于DSP处理器的片上ROM功耗优化实现

Optimization of On-chip ROM Power Consumption Based on DSP Processor

数字信号处理器(Digital Signal Processing,DSP)芯片用于手持式设备,功耗是其核心参数;DSP因ROM具有高的可靠性而使用其对固化的bootloader,科学函数库,功能函数库以及主应用程序进行存储,其功耗的大小对整个芯片产生了较大的影响;针对芯片中ROM被频繁访问产生较大功耗的问题,提出了对ROM存储空间进行结构优化和对其存储空间进行地址重组优化及对读数据时序结构进行优化的低功耗优化方法,达到了在不影响DSP性能的前提下降低功耗的目的;DSP已经流片并改版,最终减小DSP整体功耗约11.3%。

Digital Signal Processing(DSP)chips are used for handheld devices,and power consumption is the core parameter.Due to the high reliability of ROM,this DSP uses it to store the curing bootloader,scientific function library,functional function library and main application program,and its power consumption has a great impact on the whole chip.In order to solve the problem of high power consumption caused by frequent access of ROM in the chip,a low power optimization method is put forward to optimize the structure of ROM storage space,optimize the address recombination of ROM storage space and optimize the timing sequence structure of read data,so as to reduce the power consumption without affecting the performance of DSP.This DSP has been streamed and revised to reduce the total power consumption of DSP by about 11.3%.