基于FPGA的卷积神经网络并行加速器设计

Parallel accelerator design for convolutional neural networks based on FPGA

近年来,卷积神经网络在许多领域中发挥着越来越重要的作用,然而功耗和速度是限制其应用的主要因素。为了克服其限制因素,设计一种基于FPGA平台的卷积神经网络并行加速器,以Ultra96-V2为实验开发平台,而且卷积神经网络计算IP核的设计实现采用了高级设计综合工具,使用Vivado开发工具完成了基于FPGA的卷积神经网络加速器系统设计实现。通过对GPU和CPU识别率的对比实验,基于FPGA优化设计的卷积神经网络处理一张图片的时间比CPU要少得多,相比GPU功耗减少30倍以上,显示了基于FPGA加速器设计的性能和功耗优势,验证了该方法的有效性。

In recent years,convolutional neural network plays an increasingly important role in many fields.However,power consumption and speed are the main factors limiting its application.In order to overcome its limitations,a convolutional neural network parallel accelerator based on FPGA platform is designed.Ultra96-v2 is used as the experimental development platform,and the design and implementation of convolutional neural network computing IP core adopts advanced design synthesis tools.The design and implementation of convolutional neural network accelerator system based on FPGA is completed by using vivado development tools.By comparing the recognition rate of GPU and CPU,the convolutional neural network based on FPGA optimized design takes much less time to process a picture than CPU,and reduces the power consumption of GPU by more than 30 times.It shows the performance and power consumption advantages of FPGA accelerator design,and verifies the effectiveness of this method.