新型CMOS大数逻辑门电路的设计

Design of novel CMOS majority logic gate

一步大数逻辑可译码(One-Step Majority Logic Decodable,OS-MLD)可用来促进存储器恢复单粒子翻转引起的软错误.其中,大数逻辑门(Majority Logic Gate,MLG)在译码电路中起着非常重要的作用,然而目前已提出的MLG电路需要极大的硬件开销.针对这一问题,本文提出一种新型MLG电路,该电路由PMOS管构成的上拉网络、NMOS管构成的下拉网络以及一个反相器构成.利用Cadence软件进行仿真验证可知,该电路不仅能够实现正常的大数逻辑功能,在功耗、延时、面积等性能指标方面也均优于现有的电路结构.同时,将所设计的MLG应用到OS-MLD中,结果表明,所提出的MLG对于该编码应用是有效的.

One-Step Majority Logic Decodable(OS-MLD)can be used to protect memory from soft errors caused by single-particle flips in where Majority Logic Gate(MLG)plays an important role in the decoders.However,the existing MLG circuits require more hardware overhead.This paper proposes a new type of MLG circuit which consists of a PMOS pull-up network,an NMOS pull-down network,and an inverter.Simulation verification with Cadence software shows that the proposed circuits not only correctly perform majority logic,but also feature lower overhead in terms of power consumption,delay,and area,compared with the existing MLG circuits.At the same time,the designed MLG is applied to OS-MLD,and the results show that the proposed MLG is effective for this coding application.