新型串行融合Reed-Solomon码译码器设计

Design of a Novel Serial United Reed-Solomon Decoder

针对流水线结构融合里德-所罗门(Reed-Solomon,RS)码译码器时序中存在大量空闲等待时间的问题,提出了一种新型串行融合RS码译码器架构。为消除流水线阶段中的空闲等待时间,将译码器时序调整为串行结构;通过译码子模块电路复用设计了一种分时实现不同模块功能、可同时适用于随机错误译码与单段突发错误译码的mSPCF模块;提出基于mSPCF模块的串行融合RS码译码器架构,并对译码器进行了延时分析,在SMIC 0.13μm CMOS工艺库下对译码器进行了电路逻辑综合。仿真结果表明:与流水线结构融合译码器相比,所提译码器可减少约9.4%的硬件资源消耗,在信噪比6.2~7.4 dB范围内发生译码随机错误和单段突发错误时,平均译码延时可分别降低约73.45%和45.65%,吞吐率分别提升约236.76%和64.49%,证明该译码器具有更优异的性能。

A novel serial united Reed-Solomon(RS)decoder is proposed to deal with the idle time that exists in the decoding process of pipeline united RS decoder.To eliminate the idle time in the pipelining stage,the timing chart of decoder is adjusted to a serial structure.Through the multiplexing design of decoding modules,a time-sharing mSPCF module is designed to realize different module functions.The mSPCF module could be utilized both in decoding random errors and single burst error.Then,a serial united RS decoder based on mSPCF module is proposed and the delay analysis of the decoder is carried out.Furthermore,the decoder is synthesized by SMIC 0.13μm CMOS technology library.The simulation results show that compared with the pipeline united RS decoder,the proposed decoder can reduce hardware resource consumption by about 9.4%.For decoding random errors and single burst error in the range of 6.2-7.4 dB SNRs,the average decoding delay can be reduced by 73.45%and 45.65%,respectively,and the throughput can be increased by 236.76%and 64.49%,respectively.In conclusion,the proposed serial united RS decoder has better performance and more advantages in practical applications.