晶圆级导通电阻测试精度的改进方法

Improvement Methods for Wafer Level on-Resistance Test Accuracy

针对晶圆级导通电阻测试误差过高,满足不了低压金属氧化物半导体场效应晶体管(MOSFET)毫欧级导通电阻的测试精度要求,给产品晶圆测试规范的制定及品质监控带来困扰的问题,提出了晶圆级导通电阻测试精度的改进方法。基于开尔文法电阻测试理论,具体分析了晶圆级导通电阻测试原理,且得出其测试精度不高的根本原因是减薄背金后粗糙不平的硅片背面与测试机的承片台的非充分接触而引入了毫欧级接触电阻。提出3种相应改进测试精度的方法,单相邻芯片辅助的测试方法、双相邻芯片辅助的测试方法和正面漏极测试窗的测试方法。经过验证,3种方法均能将毫欧级导通电阻测试误差控制到小于10%,实现低压MOSFET晶圆级导通电阻参数的有效监测。

In view of the problem that the test error of wafer level on-resistance was too high to meet the milliohm level on-resistance test accuracy requirements of low-voltage metal oxide semiconductor field effect transistor(MOSFET),which brought troubles to the formulation of product wafer test specification and quality control,the improvement methods of wafer level on-resistance test accuracy were proposed.Based on the theory of Kelvin method for resistance test,the test principle of wafer level on-resistance was concretely analyzed.The primary reason of its low test accuracy was that the milliohm level contact resis-tance caused by the inadequate contact between rough backside of Si wafer after back grinding and back metal and the CP tester chuck.Three methods for improving the test accuracy were proposed,single neighbor chips test mode,double neighbor chips test mode and top drain test pads mode.After verification,the test error of milliohm on-resistance can be controlled to less than 10%by the three methods,and the effective monitoring of wafer level on-resistance parameters of low-voltage MOSFET is realized.