一种模式可配置的单精度浮点乘法器设计

Design of a mode-reconfigurable floating-point multiplier

提出了一种模式可配置的单精度浮点乘法器设计方案。利用90 nm互补金属氧化物半导体(complementary metal oxide semiconductor,CMOS)工艺设计了基于原码一位乘法、基4-Booth算法和Wallace树型算法等3种常用定点数乘法的浮点乘法器,测试了3种乘法器的性能。在乘法器的尾数乘法部分添加模式选择模块,根据应用场景对频率、功耗和面积3个性能的不同需求选择和切换相应的算法,以满足不同应用对对处理器性能的要求。实验结果表明,与ifpmul32方法相比,所提设计的延时降低了57%,最低功耗降低了76.6%。与粗粒度可重构处理器实现的浮点乘法器相比,计算一次浮点乘法所需时钟周期数平均减少了87.3%。

A design scheme of single-precision floating-point multiplier with configurable mode is proposed.Floating point multipliers based on the original code one-bit multiplication,4-Booth algorithm and Wallace tree algorithm are designed and implemented in 90 nm complementary metal oxide semiconductor(CMOS)process.The performance of the three multipliers is tested.A mode selection module is added to the mantissa multiplication part of the multiplier.According to the different requirements of the application scenario for the three performances of frequency,power consumption and area to select and switch the corresponding algorithm,to meet the requirements of different applications for processor performance.The experimental results show that the proposed method can reduce the latency and power dissipation by 57%and 76.6%respectively in comparison with ifpmul32,and average clock cycles needed to finish one multiplication decreases 87.3%compared to a implementation on coarse-grained reconfigurable processors.