统一渲染架构GPU中可配置二级Cache设计

Design of configurable L2 cache for unified rendering architecture GPU

针对统一渲染架构图形处理器(graphics processing unit,GPU)在不同应用场景下的缓存需求,提出了一种大小及数目可配置的二级高速缓存(L2 Cache)设计方案。单一L2 Cache设计采用4路组相联结构,使用改进的伪最近最少使用PLRU-0(modified pseudo-LRU-0)算法作为替换算法,利用哈希选择算法控制不同配置模式的切换,最终实现了128 kB、256 kB、512 kB三种L2 Cache大小及数目的配置模式。实验结果表明,与不可配置L2 Cache的方案相比,所提设计方案的GPU中缓存结构性能较好。

Aiming at the cache requirements of the unified rendering architecture graphics processing unit(GPU)in different application scenarios,a configurable size and number of secondary cache(L2 Cache)design solutions are proposed.A single L2 Cache design adopts a 4-way group-associated structure,using PLRU-0(modified pseudo-LRU-0)as a replacement algorithm,and using a hash selection algorithm to control the switching of different configuration modes,finally,the configuration modes of 128 KB,256 KB and 512 KB three configuration modes of L2 Cache size and number are realized.Experimental results show that compared with the non-configurable L2 Cache solution,this structure can effectively improve the performance of the cache structure in the GPU.