基于VerilogHDL的IIC总线竞争实现

Implementation of IIC Bus Competition Based on VerilogHDL

本文依据IIC(Inter-Integrated Circuit)通讯协议,利用硬件描述语言VerilogHDL在Synopsis平台上设置并测试了多机竞争场景,为总线竞争提供统一时钟,消除总线竞争数据传输时潜在的数据采集错位等问题,实现数据总线SDA和时钟总线SCL的正常读写,并保证了总线挂载设备间的互不干扰,有效规避数据冲突或丢失,使设计对挂载众多IIC设备的总线竞争的场景具备灵活适应性。并在Verdi3仿真环境下,验证了设计的正确性,且在测试实验中用示波器截图验证。

Based on the IIC(Inter Integrated Circuit)Communication Protocol,using Verilog HDL to test and set the multi-machine competition scenario on synopsis platform,providing synchronized clock for bus competition,eliminates potential data mis-sampling during data transmission of the bus competition and realizes the ritual operation of reading and writing over data bus SDA and clock bus SCL,and ensures the mutual non-interface between bus mounted devices,effectively averting data conflict or data loss,as to make this design more flexible and adaptable for multi-mounted IIC bus utilizing.The correctness of the design is verified by Verdi3 simulator in the VerilogHDL simulation environment,and the oscilloscope screenshots explored in the verification test support the correctness of the design.