多片FPGA动态加载方案实现

The Implementation of multiple FPGAs dynamic loading

FPGA通常与FLASH配合使用,可以在上电之后自动加载并执行特定功能的逻辑程序。这种方式简单可靠,但无法实现系统在不掉电的情况下更换FPGA内部逻辑。针对这一问题,本文实现一种基于CPU与CPLD配合动态构造FPGA程序的使用方式,此方式使得FPGA在不掉电的条件下加载并执行新的程序,适合FPGA的远程配置及自动化应用场景。本系统利用FPGA提供的动态构造接口,使得CPU与CPLD相配合产生满足FPGA的构造接口的时序,从而实现FPGA的程序更新。

FPGA is usually used with flash,so it can automatically load and execute logic programs with specific functions after power on.This method is simple and reliable,but FPGA can not update internal logic without power down.In order to solve this problem,this paper implements a method of dynamic construction of FPGA program based on CPU and CPLD,which makes FPGA load and execute new logic without power down,which is suitable for remote configuration and automatic application scenarios of FPGA.This system makes CPU and CPLD cooperate to produce the timing that meets the configure interface of FPGA,so as to update the inner logic of FPGA without power down.