期刊文献+

The past and future of multi-gate field-effect transistors:Process challenges and reliability issues 被引量:1

下载PDF
导出
摘要 This work reviews the state-of-the art multi-gate field-effect transistor(MuGFET)process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices.Owing to the 3D wrapped gate structure,MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region.As the Si CMOS technology pioneers to sub-10 nm nodes,the process challenges in terms of lithography capability,process integration controversies,performance variability etc.were also discussed in this work.Due to the severe self-heating effect in the MuGFETs,the ballistic transport and reliability characteristics were investigated.Future alternatives for the current Si MuGFET technology were discussed at the end of the paper.More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.
出处 《Journal of Semiconductors》 EI CAS CSCD 2021年第2期29-39,共11页 半导体学报(英文版)
基金 This work was supported by Zhejiang Provincial Natural Science Foundation of China under Grant LR18F040001,LY19F040001 the Opening Project of Key Laboratory of Microelectronic Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences.
  • 相关文献

参考文献5

二级参考文献104

  • 1Huang X, Lee W C, Kuo C, et al. Sub 50-nm FinFET: PMOS. In: IEDM 1999, Washington, 1999. 67-70.
  • 2Doyle B, Boyanov B, Datta S, et al. Tri-gate fullyldepleted CMOS transistors: fabrication, design and layout. In: VLSI Tech. Symp. 2003, Kyoto, 2003. 133-134.
  • 3Jahan C, Faynot O, Casse M, et al. Ω FETs transistors with TiN metal gate and HfO2 down to 10 nm. In: VLSI Tech Symp. 2005, Kyoto, 2005. 112-113.
  • 4Park J T, Colinge J P, Diaz C H, et al. Pi-gate SOI MOSFET. IEEE Electron Dev Lett, 2001, 22:405-406.
  • 5Yang F L, Lee D H, Chen H Y, et al. 5nm-gate nanowire FinFET. In: VLSI Tech Symp. 2004, Honolulu, 2004. 196-197.
  • 6Choi Y K, King T J, Hu C. Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era. Solid State Electron, 2002, 46:1595-1601.
  • 7Lee H, Yu L E, Ryu S W, et al. Sub-5nm all-around gate FinFET for ultimate scaling. In: VLSI Tech Symp. 2006, Honolulu, 2006. 58-59.
  • 8Pelloie J L, Auberton-Herve A J, Raynaud C, et al. SOI technology performance and modeling. In: ISSCC, San Francisco, 1999. 428.
  • 9Lolivier J, Deleonibus S, Balestra F. Threshold voltage quantum simulations for ultra-thin silicon-on-insulator transistors. In: ECS Spring 2003 Proc, Paris, 2003. 379.
  • 10Suk S D, Li M, Yeoh Y Y. Characteristics of sub 5nm Tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure. In: VLSI Tech Symp, Kyoto, 2009. 142.

共引文献37

同被引文献8

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部