孪生网络跟踪算法并行计算结构研究

Parallel Computing Architecture of Siamese Network Algorithm

基于嵌入式平台的复杂背景目标跟踪技术在智能视频监控设备、无人机跟踪等领域有重要作用。卷积神经网络在跟踪问题上有准确率高、鲁棒性强的优点,但基于卷积特征的算法计算复杂度高,受嵌入式平台面积和功耗的限制,实时性难以满足嵌入式平台应用场景的需求。针对基于卷积特征的跟踪算法计算复杂度高、存储参数量大的难题,率先提出一种利用FPGA实现基于卷积神经网络的复杂背景目标跟踪硬件加速架构。该方法通过利用KL相对熵对目标跟踪算法Siamese-FC进行定点量化,设计了基于通道并行的卷积层加速架构。实验结果表明,定点量化后跟踪算法相比于原算法的平均精度损失不超过4.57%,FPGA部署后前向推理耗时仅为CPU的16.15%,功耗仅为CPU的13.7%。

Complex background target tracking algorithm based on the embedded platform plays an important role in intelligent video surveillance equipment,UAV tracking,etc.Convolutional neural network is accurate and robust on tracking problems,but the algorithm based on convolution features has high computational complexity,and is limited by the area and power consumption of the embedded platform,so the real-time performance is difficult to meet the requirements of embedded platform application scenarios.For the difficulties of high computational complexity and large number of stored parameters of the tracking algorithm based on convolutional features,a hardware acceleration architecture for complex background target tracking based on convolutional neural networks using FPGAs is proposed.A channel-parallel based convolutional layer acceleration architecture is designed by using KL relative entropy for fixed-point quantization of the target tracking algorithm Siamese-FC.The experimental results show that the average accuracy loss of the tracking algorithm after fixedpoint quantization is more than 4.57%compared with the original algorithm,the forward inference time consumption after FPGA deployment is only 16.15%,and the power consumption is only 13.7%of CPU.