CP-PLL快速入锁集成电路方案设计

Design of a Fast Lock-in IC for CP-PLL

该文基于TSMC 0.18μm RF CMOS工艺实现了一个用于加快CP-PLL锁定时间的数模混合复合结构,该复合结构主要包括两个独立单元——动态环路带宽单元及预置位反馈环。其中,两个单元的控制电路均采用全数字电路实现,并通过DC综合与ICC自动布局布线得到版图信息。经过同一CP-PLL参数环境下的对比分析,比较了包括传统结构的3种方案的锁定时间。在工作电源1.8 V下,优化后的锁定时间为1.12μs,较传统结构锁定时间提升了76.7%;整体相噪在稳态保持-103.1 dBc/Hz@1 MHz,较传统结构仅上升了0.3%。证明该复合结构能够有效降低上电启动以及跳频时的锁定时间。

Based on TSMC 0.18μm RF CMOS process,a hybrid digital analog composite structure is implemented to accelerate the locking time of charge-pump phase-locked loop(CP-PLL).The composite structure mainly includes two independent units:dynamic loop bandwidth unit and preset feedback loop.Among them,the control circuits of the two units are all digital circuits,and the layout information is obtained through DC synthesis and ICC automatic layout.Through the comparative analysis under the same CP-PLL parameter environment,the locking times of three schemes including the traditional structure are compared.Under the working power supply of 1.8 V,the optimized locking time is 1.12μs,which is 76.7%higher than that of the traditional structure;the overall phase noise keeps-103.1dBc/Hz@1MHz in the steady state,which is only 0.3%higher than that of the traditional structure.Therefore,the composite structure can effectively reduce the lock-in time of power on and frequency hopping.