摘要
基于0.7μm InP HBT工艺,设计实现了一种高功率高谐波抑制比的W波段倍频器MMIC。电路二倍频单元采用有源推推结构,通过3个二倍频器单元级联形成八倍频链,并在链路的输出端加入输出缓冲放大器,进一步提高倍频输出功率。常温25℃状态下,当输入信号功率为0 dBm时,倍频器MMIC在78.4~96.0 GHz输出频率范围内,输出功率大于10 dBm,谐波抑制度大于50 dBc。芯片面积仅为2.22 mm^(2),采用单电源+5 V供电。
Based on 0.7μm InP HBT process,a W-band frequency multiplier MMIC with high output power and high harmonic suppression has been developed.The frequency doubler unitis based on the classic active push-push structure,and the frequency-multiplier-by-eight is formed by cascading 3 frequency doubler units.A W-band buffer amplifier is connected in series at the output ends of the linkin order to increase the output power of the frequency multiplier.Under normal temperature,when the frequency multiplier is drived with input power of 0 dBm,output power of more than 10 dBm and harmonic suppression of more than 50 dBc are achieved with the output frequency range from 78.4 GHz to 96.0 GHz.The chip area is only 2.22 mm25,the single operating voltage is 5 V.
作者
刘尧
潘晓枫
程伟
王学鹏
姚靖懿
陶洪琪
LIU Yao;PAN Xiaofeng;CHENG Wei;WANG Xuepeng;YAO Jingyi;TAO Hongqi(Science and Technology on Monolithic Integrated Circuits and Module Laboratory,Nanjing Electronic Devices Insti-tute,Nanjing,210016,CHN)
出处
《固体电子学研究与进展》
CAS
北大核心
2021年第1期24-28,34,共6页
Research & Progress of SSE