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导热金刚石同大尺寸芯片的低温烧结银连接工艺 被引量:1

Low-temperature Sintering Silver Joining Process of Thermal Conductive Diamond and Large-size Chip
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摘要 通过高导热银浆实现了连接大面积(>100 mm^(2))半导体硅片和金刚石的低温低压烧结技术。通过对金刚石表面镀覆金属薄膜,增强同烧结银界面处固态原子扩散,开发了商用烧结银膏在200℃下低温烧结工艺,得到金刚石-硅的均匀连接界面,计算得到孔隙率约为9.88%,中间烧结银层等效热阻约为1.38×10^(-5)m^(2)·K/W。 The low-temperature and low-pressure sintering technology for connecting large-area(>100 mm^(2))semiconductor silicon wafers and diamond through high thermal conductivity silver paste was realized in this paper.The surface was coated with a metal film to enhance the diffusion of solid atoms at the interface.The commercial silver paste was sintered at a low temperature of about200℃to obtain an uniform connection interface of diamond-silicon bonding.The calculated porosity is about 9.6%,and the equivalent thermal resistance of the middle-sintered silver layer is about 1.38×10^(-5)m^(2)·K/W.
作者 赵柯臣 赵继文 代兵 张旭 郭怀新 孙华锐 朱嘉琦 ZHAO Kechen;ZHAO Jiwen;DAI Bing;ZHANG Xu;GUO Huaixin;SUN Huarui;ZHU Jiaqi(National Key Laboratory of Science ami Technology on Advanced Cotnposites iti Special Environments,Harbin Institute of Technology,Harbin,150080,CHN;Ministry of Industry and Information Technology Key Laboratory of Micro-nano Optoelectronic Information System,Harbin Institute o f Technology,Shenzhen,518055,CHN;Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing Electronic Devices Institute,Nanjing,210016,CHN)
出处 《固体电子学研究与进展》 CAS 北大核心 2021年第1期65-68,共4页 Research & Progress of SSE
基金 国家自然科学基金杰出青年基金资助项目(51625201) 国家自然科学基金资助项目(5207021126) 国防重点实验室基金资助项目(614280303020418)。
关键词 低温烧结银 芯片散热 金刚石 大尺寸连接 low-temperature sintered silver chip heat dissipation diamond large-size connection
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  • 1顾勇,王莎鸥,赵建明,胡永达,杨邦朝.高密度3-D封装技术的应用与发展趋势[J].电子元件与材料,2010,29(7):67-70. 被引量:6
  • 2梁红兵.中国半导体创新产品和技术特刊[N].中国电子报.2010.
  • 3诸玲珍.中国半导体创新产品和技术特刊[N].中国电子报.2011.X.
  • 4李映.全国集成电路行业工作会议特刊[N].中国电子报.2011.
  • 5于燮康.联合攻关完善本土IC封测产业链[N].中国电子报.2011.
  • 6李映.电子发展基金"十一五"成果特刊[N].中国电子报.2011.
  • 7Baliga B J.The future of power semiconductor devicetechnology[J].Proc.IEEE,2001,89(6):822-832.
  • 8OettingerFF,Blackburn D L.SemiconductorMeasurement Technology:Thermal ResistanceMeasurements [ M].Washington DC,U S:Department of Commerce,1990.
  • 9Otiaba K C,Bhatti R S,Ekere N N,et al.Numericalstudy on thermal impacts of different void patterns onperformance of chip-scale packaged power device[J].Microelectronic Reliability,2012,52:1409-1419.
  • 10Montano M,Garcia J.Novel process techniques toreduce voids in solder thermal interface materials usedfor flip-chip package applications [C]// ASME Conf.Summer Heat Transfer,2005:2369-2374.

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