基于FPGA的LDPC编码器设计与实现

Design and implementation of LDPC encoder based on FPGA

设计了一种用于近地空间通信的CCSDS标准下编码速率为7/8的(8176,7154)低密度奇偶校验(Low density parity check,LDPC)编码器。基于LDPC编码理论,完成了基于现场可编辑逻辑门阵列(Field-programmable gate array,FPGA)的编码算法设计。利用LDPC生成矩阵的特点,引入循环移位寄存器作为编码电路核心,采用移位寄存器加累加器(Shift-register-adder-accumulator,SRAA)结构实现了矩阵乘法的快速运算,从而构建了以部分并行编码电路为核心的编码模块。此外,还设计了串口输入输出模块、随机存储模块和控制模块,共同组成了编码器系统。最后,利用FPGA完成硬件设计,并进行了仿真和实验验证。结果表明,所设计的LDPC编码器测试结果与理论结果具有一致性。因而该编码系统具有实用性,且设计方法简单、高效。

A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.