ANT系列分组密码算法的FPGA高速实现

High-speed implementation of ANT series block cipher algorithm on FPGA

ANT系列分组密码算法是一种轻量级密码算法,针对ANT-128/128算法,使用Verilog HDL分别对密钥扩展模块、加密模块在Quartus Ⅱ 15.0中进行工程实现,并采用46级全流水线结构进行高速优化。在Cyclone V系列5CGXFC7D6F31C7ES芯片中综合结果表明,工程实现结果与标准向量值一致,两模块逻辑利用率分别仅占总资源的3%及7%,且基于流水线优化后的加解密模块工作频率最高可达339 MHz,数据吞吐率最高可达43 Gb/s,能够满足大部分高速加密系统的需求。

ANT series block cipher algorithm is suitable for lightweight implementation and convenient for side channel protection.For ANT-128/128 algorithm, Verilog HDL is used to implement the key expansion module and encryption module in Quartus Ⅱ 15. 0, and a 46-level pipeline structure is adopted for high-speed optimization. Further, the pipeline structure was used for high-speed optimization. The comprehensive results in chip 5CGXFC7D6F31C7ES of Cyclone V show that the implementation results are consistent with the standard vector value. The logic utilization ratio of the two modules only accounts for 3 % and 7 % of the total resources respectively. The working frequency of the encryption and decryption module based on pipeline structure can reach up to 339 MHz and the data throughput rate can reach up to 43 Gbps.