一种新颖的多值基准输出缓冲器设计

Design of a Novel Multivalued Reference Voltage Output Buffer

对比分析了不同结构的传统多值基准输出缓冲器,提出了一种新颖的多值基准输出缓冲器结构。采用PMOS输出结构提高了输出电压摆幅,利用低输出阻抗结构加快了瞬态响应速度,解决了传统结构无法兼具高输出与快响应的矛盾,电路功耗低、易补偿。基于0.15μm标准CMOS工艺,用Hspice软件对电路进行仿真。仿真结果表明,当电源电压为5 V、温度为25℃时,输出电压上限可达4.82 V;当补偿电容取3 pF时,相位裕度达到86°;当输入电压为1.2 V、输出电压为4.5 V、输出电流扰动变化量为100 nA时,瞬态响应时间为4μs;静态电流仅为7μA。

The traditional multivalued reference voltage output buffers with different structures were compared and analyzed, and a novel one with low power consumption and easy compensation was proposed. The PMOS output structure and the low output impedance structure were used in the novel circuit to obtain both the higher output voltage swing and the faster transient response speed. The proposed circuit was simulated and verified in a 0.15 μm standard CMOS process with the Hspice. The simulation results showed that when the power supply voltage was 5 V and the temperature was 25℃, the output voltage upper limit could reach 4.82 V. When the value of the compensation capacitor was 3 pF, the phase margin was 86°. Under the conditions of 1.2 V input voltage, 4.5 V output voltage and 100 nA output current disturbance variation, the transient response time was 4 μs. The quiescent current was only 7 μA.