一种高线性低功耗射频鉴频器的设计

Design of a high⁃linearity low⁃power RF frequency detector

设计了一款用于射频接收系统的低功耗高线性高灵敏度斜率鉴频器,电路采用65 nm CMOS工艺,与传统的基于单带通滤波器的结构相比,双带通滤波器的结构有效提高了鉴频器的解调线性度;引入单端中频放大器降低了减法器失调电压对鉴频灵敏度的影响。仿真结果表明,所设计的基于双带通滤波器结构的鉴频器在1 V供电电压下,功耗为1 mW,鉴频灵敏度为-70 dBm。

A high⁃linearity,low⁃power slope frequency detector,with high demodulation sensitivity,is implemented in 65 nm CMOS for RF receiver systems.Compared to the conventional single⁃ended architecture with a Band⁃Passed Filter(BPF)for FM⁃to⁃AM conversion,the present design based on dual BPFs,achieves better demodulation linearity.The embedded single⁃ended Intermediate⁃Frequency(IF)amplifiers greatly suppress the inverse influence of the offset voltage from the subtractor on demodulation sensitivity.Simulated results show that the present design based on dual BPFs from a 1 V supply voltage successfully demodulate the-70 dBm RF FM signal,with the power dissipation of 1 mW.