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一种100 G EPON系统RS编码器设计与实现 被引量:2

Design and implementation of RS encoder for 100 G EPON system
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摘要 提出了一种用于100 G以太网无源光网络(Ethernet Passive Optical Network,EPON)通信系统的里德-所罗门(Reed-Solomon,RS)编码器设计方法。100 G EPON通信系统由4个25 G EPON通信子系统组成,针对每一路25 G通信系统,采用纠错能力强、可靠性高的RS(1023,847)码组作为编码器的码型。根据编码器码组类型等参数,以及输入数据更新周期与位宽等特性,计算出编码电路的并行度。利用多路切换技术、数据并行化计算等高速设计技术,提出了一种可用于单通道的高速RS(1023,847)编码器设计方案。实际组网测试结果表明,设计的单通道RS(1023,847)编码器最高数据吞吐率可达25 Gbit/s,电路的最高时钟频率可达390.625 MHz,4路单通道编码器可实现最高数据吞吐率100 Gbit/s的RS编码,能够满足100 G EPON系统要求。 A Reed-Solomon(RS)encoder design method for 100 G ethernet passive optical network(EPON)communication systems is proposed.The 100 G EPON communication system consists of four 25 G EPON communication subsystems.For each 25 G communication system,RS(1023,847)code group with strong error correction ability and high reliability is adopted as the code type of the encoder.The parallelism of the encoding circuit is calculated according to the parameters such as the type of the encoder code set,the characteristics of the update period and bit width of the input data.A design scheme of high-speed RS(1023,847)encoder which can be used in a single channel is proposed by using high-speed design techniques such as multiplexing and data parallelization.The results of practical networking test show that the highest data throughput rate that the designed single-channel RS(1023,847)encoder can achieve is 25 Gbit/s,the highest clock frequency of the circuit can reach 390.625 MHz,and the highest data throughput rate that the four-way single-channel encoder can achieve for RS encoding is 100 Gbit/s,which can meet the requirements of 100 G EPON system.
作者 杜慧敏 张英杰 张丽果 DU Huimin;ZHANG Yingjie;ZHANG Liguo(School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China)
出处 《西安邮电大学学报》 2021年第1期46-53,共8页 Journal of Xi’an University of Posts and Telecommunications
基金 国家重点研发计划项目(2019YFB1803600)。
关键词 REED-SOLOMON码 伽罗华域 并行编码 并行度 前向纠错码 EPON通信系统 Reed-Solomon code Galois field parallel coding degree of parallelism forward error correction code EPON communication system
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  • 1严来金,李明,王梦.RS(255,223)译码器的设计与FPGA实现[J].微计算机信息,2005,21(1):148-149. 被引量:12
  • 2罗朝霞,张高记.CDMA系统中反向链路卷积编码器的CPLD实现[J].西安邮电学院学报,2005,10(1):58-61. 被引量:1
  • 3戴小红,潘志文.Reed-Solomon编译码器的设计与FPGA实现[J].现代电子技术,2006,29(3):119-121. 被引量:5
  • 4Junho Cho. Efficient Software-Based Encoding and Decoding of BCH Codes [ J ]. IEEE TRANSACTIONS ON COMPUTERS, 2009,58(7) : 878-889.
  • 5王进宏.BCH(15,7,5)纠错译码的MATLAB实现.华东理工学院学报,2006,29(1):97-102.
  • 6Lee Hanho.High speed VLSI architecture for parallel reed solomon decoder[J].IEEE Trans on VLSI System,2003,11(2):288-294.
  • 7Shao H M, Reed I S.On the VLSI design of a pipeline reed solomon decoder using systolic arrays[J].IEEE Trans on Computers, 1998,37(10).
  • 8Xilinx Co.Virtex-4 family overview[S].2006-10-10.
  • 9Xilinx Co.Virtex-4 user guide[S].2007-04-10.
  • 10金国平.星用双模应答机中纠错编码技术的研究[D].长沙:国防科技大学,2004:4-18,40.58.

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