5G LDPC码译码器实现

On the Implementation of 5G LDPC Decoder

该文介绍了5G标准中LDPC码的特点,比较分析了各种译码算法的性能,提出了译码器实现的总体架构:将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形,为译码器的主体;低信噪比译码器主要针对低码率、低信噪比下的高性能译码,处理一些极限情形下的通信,对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践,给出了FPGA综合结果和吞吐率分析结果。

This paper focuses on the Low-Density-Parity-Check(LDPC)decoder for 5G New Radio(NR)specification.After introducing the characteristics of the LDPC code in 5G NR,the performance of different decoding algorithms are compared,and then the overall architecture of the decoder is proposed.In the proposed architecture,the decoder is divided into high-speed decoder and high-performance decoder.The high-speed decoder is intended for high-rate and high throughput decoding,while the high-performance decoder is used for low-rate decoding under low Signal-to-Noise-Ratio(SNR)scenarios,which is for communications under extremely bad situations,and does not need a high throughput.The design is implemented on Field Programmable Gate Array(FPGA)and the results are shown.