基于FPGA的多路抢答器设计与仿真

Design and simulation of multi-channel snswerer based on FPGA

针对现有抢答器性能不稳定、不精确等问题,以FPGA芯片EP2C35F672C8为实现载体,通过QUARTUSII9.0和VHDL设计并实现一款新颖的八人四组抢答器。采用VHDL设计各模块并生成逻辑符号图,按照抢答器的工作原理,将逻辑符号图级联构成抢答器的顶层电路,通过功能仿真、下载验证目标文件。实验结果表明,该抢答器能够正确显示抢答选手组号,可以应用在各类竞赛性质的场合。与传统的PIC或者单片机设计方案相比,简化了接口和控制,操作方便灵敏度高,能有效提高系统的可靠性。

Aiming at the problems of unstable and inaccurate performance of existing answering devices,FPGA chip EP2 C35 F672 C8 is used as the implementation carrier,and a novel eight-person four-group answering device is designed and implemented through QUARTUSII9.0 and VHDL.Using VHDL to design each module and generate logic symbol diagram,according to the working principle of the answerer,the logic symbol diagram is cascaded to form the top circuit of the answerer,and the target file is verified through functional simulation and download.The experimental results show that the answering device can correctly display the group number of the answering players,and can be used in various competition situations.Compared with the traditional PIC or SCM design scheme,the interface and control are simplified,the operation is convenient and the sensitivity is high,which can effectively improve the reliability of the system.