功率硬件在环仿真系统的建模与稳定性分析

MODELING AND STABILITY ANALYSIS OF POWER HARDWARE-IN-THE-LOOP SIMULATION SYSTEM

在功率硬件在环(power hardware-in-the-loop,PHIL)仿真系统中,考虑到采样延迟和离散化误差会导致PHIL系统失稳失真,提出一种通用的PHIL系统离散域建模方法和基于离散D分割的稳定边界计算方法。和传统的连续域模型相比,该文所提出的离散域模型能反映出延时和离散化导致的PHIL仿真系统高频失稳,说明了PHIL系统可模拟实物系统的阻抗范围小于连续域模型。功率硬件在环实验证明所提的PHIL仿真系统建模方法和稳定边界计算方法的正确性,验证了仿真步长和阻抗匹配对PHIL系统稳定边界的影响,表明了现场可编辑逻辑门阵型(FPGA)小步长仿真功率硬件在环仿真可增加PHIL系统的稳定边界,扩大阻抗选择范围,有助于模拟弱网和逆变器交互特性。

Considering the instability and distortion of power hardware-in-the-loop simulation(PHILs)system caused by the sampling delay and discretization error,a unified discrete-domain model for PHIL system and a D-segmentation-based stable boundary calculation method are proposed in this paper. Compared with the traditional continuous-domain model,a high-frequency instability of PHILs caused by delay and discretization is discovered by this proposed model and a reduced impedance range of hardware under test(HUT)in PHILs is indicated by the presented stable boundary. The PHILs experiments verify the correctness of the proposed modeling method and the stability boundary and demonstrate the influence of simulation step and impedance matching on the stability of PHILs.The results show that the FPGA-based small-step PHILs is an effective tool to simulate the interaction between weak grid and inverter because of an increasing stable boundary and enlarged the impedance range of HUT.