面向功耗优化的CMOL电路容错映射

Power Oriented Optimization for the Defect-Tolerant Mapping of CMOL Circuits

针对CMOS/纳米线/分子混合(CMOL)电路的缺陷导致电路功耗增加这一问题,提出基于单元限用的容错映射方法.首先建立缺陷对的功耗模型,分析常连缺陷对的映射模式对功耗的影响;然后通过高功耗单元的限用与功耗约束的设置,以减少高成本映射模式带来的功耗开销;最后采用改进的遗传算法完成电路容错映射. ISCAS标准测试电路的实验结果表明,所提方法在成功容错映射的基础上,有效地减少了电路的功耗与面积,同时对求解速度也有较好的优化.

Aiming at the power consumption increase problem from the defects of CMOS/nanowire/molecular hybrid(CMOL)circuits,a defect-tolerant mapping method based on cell limitation is proposed.First,the power consumption model of defect pairs is established and the effect of different mapping patterns of the defect pairs on power consumption is analyzed.Then,the use of power hungry cells is restricted and the power consumption constraint is set to reduce the power consumption overhead caused by the high cost mapping patterns.Finally,the modified genetic algorithm is chosen to implement the defect-tolerant mapping of CMOL circuits.The ISCAS benchmarks are tested for verification.The experimental results demonstrated that the proposed method effectively reduces the power consumption and area of CMOL circuits on the basis of successful defect-tolerance,with better optimization of solution speed.