基于FPGA技术的8B/10B信道编码设计

Design of 8B/10B channel coding based on FPGA

该文在分析8B/10B编码原理的基础上,设计了改进型8B/10B编码方案。该编码在完成高速数据信道编码功能的同时,可另外提供一路实时低速信道。基于FPGA技术采用查表法实现了改进型编解码电路,通过仿真验证了该编码方案的有效性,并在Spartan6系列FPGA中进行了综合测试。结果表明,此编解码方法占用的FPGA逻辑资源少,编解码速度可达到上百MB/s。

Based on analyzing the principle of 8B/10B coding, an improved 8B/10B coding is designed, which can provide another real-time low-speed channel with encoding the high-speed data. Based on FPGA technology, the lookup table method is used to realize the circuit of the improved encoding and decoding. The effectiveness of the encoding scheme is verified by simulation, and the synthesis is carried out in Spartan6 series FPGA. The results show that this design takes up less FPGA logic resources, and the speed of encoding and decoding can reach hundreds of MB/s.