采用Qsys实现的时间管理系统

Time management system realized by Qsys

设计在Qsys系统上搭建硬件的最小系统,依据功能按模块进行设计与实现,并通过加入液晶IP核和外围电路实现用户交互。设置锁相环控制SDRAM芯片,实现系统内容的存取,最终将各个模块整合,再在软核内进行数据处理和逻辑运算,实现时间管理的功能。设计给出整体的软硬件设计方案,以及FPGA芯片与外围电路的详细接口示意图,有效利用了Qsys强大的设计能力和直观易用的接口,充分发挥FPGA片上资源丰富、处理速度快且可移植性好的优点,在教学和日常生活中均有实际应用价值。

The minimum system of hardware built on the Qsys is designed.The system is designed and divided into some modules according to the functions,and then the user interaction is realized by adding the LCD IP core and peripheral circuit.By setting phase⁃locked loop,SDRAM chip is controlled to access system content.All the modules are integrated together.The data processing and logical operation are carried out in the soft core to realize the function of time management.In the design,the overall software and hardware design scheme,and the detailed interface diagram between FPGA chip and peripheral circuit are given.The powerful design ability and intuitive easy⁃to⁃use interface of Qsys are effectively utilized.The full play is given to the advantages of FPGA chip,such as the advantages of rich resources,fast processing speed and good portability,which has practical application value in teaching or daily life.